Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

Abstract With the development of neural signal acquisition systems, spike-sorting algorithms have been paid full attention. As one most extensively used spike-detection algorithms, a 4-bit absolute-value detector is designed in paper, which comprises three types architecture. The first design using combinational logic circuit through truth table absolute value 2′s complement format and comparator; second combination series half adders transmission gates third consists by cascade adders. Then paper compares total number stages consuming transistors each circuit, finally chooses has five 74 consumption, as object following optimization critical path delay energy consumption. gate sizing, optimized about 43.05 t p0 . original consumption under minimum 49.88C, 1.5x 30.35C reduced 39.16%. processing functional realization detectors can both benefit from presented this work.